It is recommended to first read through the Transistors theory page. In the world of digital electronics, there are two logic levels that a signal can reside in: either a HIGH/(1)/ON or a LOW/(0)/OFF. This is also known as the binary system. This page focuses on logic levels associated with the CMOS architecture, since it is a relatively new technology in comparison to TTL.

Figure 1 represents an ideal digital signal based on the CMOS standard.

Figure 1: Logic (ideal)

This signal is ideal, based on three reasons:

  • Exact voltages: The signal possesses only two voltages: 0 V and 3.3 V.
  • No rise/fall time: The transition from 0 V to 3.3 V and from 3.3 V to 0 V is instantaneous.
  • No noise: The signal possesses no other voltage level.

Depending on the communication method, such as I2C, UART, SPI etc., a signal received/transmitted will possess certain characteristics. Figure 2 represents a non-ideal scenario of an I2C receiver (slave), OLED display, receiving a signal/command from an I2C transmitter (master), MCU.

Figure 2: Logic (non-ideal)

The receiver interprets the signal as either LOW or HIGH, based on the following criterion:

  • VOH(min) represents the minimum voltage the transmitter can transmit for an outgoing signal to be read as HIGH by the receiver.
  • VIH(min) represents the minimum voltage the receiver can receive for an incoming signal to be read as HIGH.
  • VNH represents the noise margin between VIH(min) and VOH(min).
  • VOL(max) represents the maximum voltage the transmitter can transmit for an outgoing signal to be read as LOW by the receiver.
  • VIL(max) represents the maximum voltage the receiver can receive for an incoming signal to be read as LOW.
  • VNL represents the noise margin between VIL(max) and VOL(max).

The following voltages are noticeable in this signal:

  • Vmax represents the highest voltage possessed by the incoming signal to the ground (GND).
  • Vmin represents the lowest voltage possessed by the incoming signal to GND.
  • Vtop represents the stabilised voltage of an incoming signal at the HIGH level.
  • Vbase represents the stabilised voltage of an incoming signal at the LOW level.
  • tr represents the rise-time of the signal, i.e., from VIL(max) to VIH(min).

Depending on the communication method, there is a maximum allowable rise time. The rise time is typically taken from 10 % to 90 % of the supply voltage due to two main reasons. The first reason is to allow measuring equipment, such as an oscilloscope, enough time to take the first measurement in addition to avoiding any noise that may be present at the very beginning. The second reason is due to the fact that no system can reach 100 % of the supply voltage, such as the exponential charging characteristic of a capacitor. Ringing, as seen at Vmax and Vmin, is an imperfection as a result of a phenomenon called parasitic inductance. Peaks and troughs like this may pass the absolute maximum and minimum thresholds, respectively. Any signals that spike into the intermediate region can result in a floating value between LOW and HIGH, which in turn can result in corrupt data. Managing imperfections of digital communication is essential in minimising the probability of data corruption. The manufacturer datasheet for CMOS-based chips will specify at which voltage a logic LOW or HIGH will be registered. These voltages vary from chip to chip and are not universal.