Objective
The objective of this laboratory is to display characters on an SPI-enabled OLED display.
Preparation
The following schematic details the hardware setup.
Table 1 lists the components used in the schematic.
| ID | Component | Manufacturer Part No. | Value | Qty. |
| Base Components | ||||
| IC1 | MCU | PIC24FJ256GA702-I/SP | – | 1 |
| IC2 | Regulator | LM1117T-3.3/NOPB | 3.3V / 800mA | 1 |
| C1 & C2 | Capacitor (tantalum) | TAP106K025SRW | 10uF / 25V | 2 |
| C3 & C4 | Capacitor (ceramic) | SR155C103KARTR1 | 0.01uF / 50V | 2 |
| C5 & C6 | Capacitor (ceramic) | SR155C104KARTR1 | 0.1uF / 50V | 2 |
| C7 & C8 | Capacitor (ceramic) | SR151A150JARTR1 | 15pF / 100V | 2 |
| C9 | Capacitor (ceramic) | FG16X7R1E106KRT06 | 10uF / 25V | 1 |
| Y1 | Crystal | ABL-16.000MHZ-B2 | 16MHz | 1 |
| R1 | Resistor | SFR2500001002FR500 | 10kΩ | 1 |
| R2 | Resistor | SFR2500001004FR500 | 1MΩ | 1 |
| J1 | Header (6-way) (PICkit 5) | 22-27-2061 | – | 1 |
| Additional Components | ||||
| IC3 | OLED | SSD1351 | – | 1 |
Refer to the following source code. Line #65 of the source code calls the SSD1351.h library.
/* SPI (source code) */
/* MCU: PIC24FJ256GA702 */
/* Author: Michael */
/**************************** Configuration Bits ******************************/
// FSEC
#pragma config BWRP = OFF // Boot Segment Write-Protect bit (Boot Segment may be written)
#pragma config BSS = DISABLED // Boot Segment Code-Protect Level bits (No Protection (other than BWRP))
#pragma config BSEN = OFF // Boot Segment Control bit (No Boot Segment)
#pragma config GWRP = OFF // General Segment Write-Protect bit (General Segment may be written)
#pragma config GSS = DISABLED // General Segment Code-Protect Level bits (No Protection (other than GWRP))
#pragma config CWRP = OFF // Configuration Segment Write-Protect bit (Configuration Segment may be written)
#pragma config CSS = DISABLED // Configuration Segment Code-Protect Level bits (No Protection (other than CWRP))
#pragma config AIVTDIS = OFF // Alternate Interrupt Vector Table bit (Disabled AIVT)
// FBSLIM
#pragma config BSLIM = 0x1FFF // Boot Segment Flash Page Address Limit bits (Enter Hexadecimal value)
// FOSCSEL
#pragma config FNOSC = PRIPLL // Oscillator Source Selection (Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL))
#pragma config PLLMODE = PLL96DIV4 // PLL Mode Selection (96 MHz PLL. Oscillator input is divided by 4 (16 MHz input))
#pragma config IESO = OFF // Two-speed Oscillator Start-up Enable bit (Start up with user-selected oscillator source)
// FOSC
#pragma config POSCMD = HS // Primary Oscillator Mode Select bits (HS Crystal Oscillator Mode)
#pragma config OSCIOFCN = ON // OSC2 Pin Function bit (OSC2 is general purpose digital I/O pin)
#pragma config SOSCSEL = OFF // SOSC Power Selection Configuration bits (Digital (SCLKI) mode)
#pragma config PLLSS = PLL_PRI // PLL Secondary Selection Configuration bit (PLL is fed by the Primary oscillator)
#pragma config IOL1WAY = OFF // Peripheral pin select configuration bit (Allow multiple reconfigurations)
#pragma config FCKSM = CSDCMD // Clock Switching Mode bits (Both Clock switching and Fail-safe Clock Monitor are disabled)
// FWDT
#pragma config WDTPS = PS1 // Watchdog Timer Postscaler bits (1:1)
#pragma config FWPSA = PR32 // Watchdog Timer Prescaler bit (1:32)
#pragma config FWDTEN = OFF // Watchdog Timer Enable bits (WDT and SWDTEN disabled)
#pragma config WINDIS = OFF // Watchdog Timer Window Enable bit (Watchdog Timer in Non-Window mode)
#pragma config WDTWIN = WIN50 // Watchdog Timer Window Select bits (WDT Window is 50% of WDT period)
#pragma config WDTCMX = WDTCLK // WDT MUX Source Select bits (WDT clock source is determined by the WDTCLK Configuration bits)
#pragma config WDTCLK = SYSCLK // WDT Clock Source Select bits (WDT uses system clock when active, LPRC while in Sleep mode)
// FPOR
#pragma config BOREN = OFF // Brown Out Enable bit (Brown Out Disabled)
#pragma config LPCFG = OFF // Low power regulator control (No Retention Sleep)
#pragma config DNVPEN = DISABLE // Downside Voltage Protection Enable bit (Downside protection disabled when BOR is inactive)
// FICD
#pragma config ICS = PGD1 // ICD Communication Channel Select bits (Communicate on PGEC1 and PGED1)
#pragma config JTAGEN = OFF // JTAG Enable bit (JTAG is disabled)
// FDEVOPT1
#pragma config ALTCMPI = DISABLE // Alternate Comparator Input Enable bit (C1INC, C2INC, and C3INC are on their standard pin locations)
#pragma config TMPRPIN = OFF // Tamper Pin Enable bit (TMPRN pin function is disabled)
#pragma config SOSCHP = ON // SOSC High Power Enable bit (valid only when SOSCSEL = 1 (Enable SOSC high power mode (default))
#pragma config ALTI2C1 = ALTI2CEN // Alternate I2C pin Location (SDA1 and SCL1 on RB9 and RB8)
/************************* Configuration Bits (end) ***************************/
#define FCY 16000000 // FCY = FOSC / 2 (FCY: Instruction clock cycle) (FOSC: System clock cycle)
#define D_C LATBbits.LATB11 // Data(1)/Command(0) (D_C) associated with MCU Pin #22
#define RES LATBbits.LATB10 // RES associated with MCU Pin #21
#include <libpic30.h> // Delay functions
#include <xc.h> // MCU pin mapping
#include "SSD1351.h" // Solomon Systech SSD1351 OLED library
int main(void)
{
// Set pin direction
TRISBbits.TRISB6 = 0; // MCU Pin #15 output (SPI1 SCK1OUT)
TRISBbits.TRISB7 = 0; // MCU Pin #16 output (SPI1 SDO1)
TRISBbits.TRISB12 = 0; // MCU Pin #23 output (SPI1 SS1OUT)
TRISBbits.TRISB11 = 0; // MCU Pin #22 output (D_C)
TRISBbits.TRISB10 = 0; // MCU Pin #21 output (RES)
/************************* configure MCU modules **************************/
// Analog Ports
ANSA = 0; // Disable A (PIC24FJ256GA702 datasheet p.126 Table 11-1)
ANSB = 0;
// Comparators
CM1CONbits.CEN = 0; // Disable #1 (PIC24FJ256GA702 datasheet p.310 Register 25-1)
CM2CONbits.CEN = 0;
CM3CONbits.CEN = 0;
// ADC
AD1CON1bits.ADON = 0; // Disable module (PIC24FJ256GA702 datasheet p.291 Register 24-1)
//SPI1
RPOR3bits.RP6R = 8; // Assign SCK1OUT to RP6 (MCU Pin #15) (PIC24FJ256GA702 datasheet p.152 Register 11-35)
RPOR3bits.RP7R = 7; // Assign SDO1 to RP7 (MCU Pin #16)
RPOR6bits.RP12R = 9; // Assign SS1OUT to RP12 (MCU Pin #23) (PIC24FJ256GA702 datasheet p.154 Register 11-38)
__delay_ms(100); // Delay to allow SSD1351 VDD stabilisation
RES = 0; // Reset (RES) pin LOW to clear SSD1351 registers
__delay_ms(100);
RES = 1; // RES pin HIGH to enable SSD1351 to receive commands
IEC0bits.SPI1IE = 0; // Disable General Interrupt (PIC24FJ256GA702 datasheet p.87 Table 8-2)
IEC0bits.SPI1TXIE = 0; // Disable Transfer Done Interrupt
SPI1CON1Lbits.SPIEN = 0; // Module disabled SFR modifications allowed (PIC24FJ256GA702 datasheet p.202 Register 17-1)
SPI1CON1Lbits.ENHBUF = 0; // Enhanced Buffer mode disabled
SPI1BRGL = 0; // Module operating at 8MHz (DS70005136 datasheet p.35 Eqn.3-1)
SPI1STATLbits.SPIROV = 0; // No overflow (PIC24FJ256GA702 datasheet p.207 Register 17-4)
SPI1CON1Lbits.MSTEN = 1; // Master mode
SPI1CON1Lbits.CKE = 0; // Transmit on transition from Idle clock state to Active clock state
SPI1CON1Lbits.CKP = 1; // Idle clock state HIGH
SPI1CON1Lbits.SPIEN = 1; // Module enabled
SPI1CON1Hbits.MSSEN = 1; // SS automatically driven during transmission in Master mode (PIC24FJ256GA702 datasheet p.204 Register 17-2)
SPI1CON1Hbits.FRMPOL = 0; // Slave Select is Active-LOW
/********************** configure MCU modules (end) ***********************/
OLED_Setup(); // Set operating conditions for SSD1351
OLED_Clear(); // Clear display RAM (GDDRAM) of SSD1351
__delay_ms(100); // Delay to allow setup of SSD1351
OLED_String(1,3,"SSD1351 OLED",'W'); // Write string "SSD1351 OLED" from Row 1 Column 3 in white 'W'
__delay_ms(500);
OLED_String(6,7,"Red",'R');
__delay_ms(500);
OLED_String(9,6,"Green",'G');
__delay_ms(500);
OLED_String(12,6,"Blue",'B');
__delay_ms(500);
OLED_Clear();
__delay_ms(500);
while (1)
{
OLED_String(8,6,"White",'W');
__delay_ms(500);
OLED_Clear();
__delay_ms(500);
}
return 0;
}Testing
The source code can be modified to display any message with characters listed in the SSD1351_Characters.h library.
Conclusion
The listed characters appear to display correctly on the SSD1351 OLED and thus can be used for the basis of projects.