Objective

The objective of this laboratory is to receive NMEA messages from a GNSS receiver (L86-M33) and display them using GPS software. It is recommended to go through the UART laboratory to setup the APC220 radio modules.

Preparation

The following schematic details the hardware setup.

Table 1 lists the components used in the schematic.

IDComponentManufacturer Part No.ValueQty.
Base Components
IC1MCUPIC24FJ256GA702-I/SP1
IC2RegulatorLM1117T-3.3/NOPB3.3V / 800mA1
C1 & C2Capacitor (tantalum)TAP106K025SRW10uF / 25V2
C3 & C4Capacitor (ceramic)SR155C103KARTR10.01uF / 50V2
C5 & C6Capacitor (ceramic)SR155C104KARTR10.1uF / 50V2
C7 & C8Capacitor (ceramic)SR151A150JARTR115pF / 100V2
C9Capacitor (ceramic)FG16X7R1E106KRT0610uF / 25V1
Y1CrystalABL-16.000MHZ-B216MHz1
R1ResistorSFR2500001002FR50010kΩ1
R2ResistorSFR2500001004FR5001MΩ1
J1Header (6-way)
(PICkit 5)
22-27-20611
Additional Components
C10Capacitor (ceramic)SR155C104KARTR10.1uF / 50V1
C11Capacitor (ceramic)FG16X7R1E106KRT0610uF / 25V1
IC3GNSS ReceiverL86-M331
IC4Radio moduleAPC2201
Table 1: Components

Refer to the following source code. Line #63 of the source code calls the L86-M33.h library.

/*                             GNSS (source code)                             */  
/*                            MCU: PIC24FJ256GA702                            */
/*                              Author: Michael                               */

/**************************** Configuration Bits ******************************/

// FSEC
#pragma config BWRP = OFF                                                       // Boot Segment Write-Protect bit (Boot Segment may be written)
#pragma config BSS = DISABLED                                                   // Boot Segment Code-Protect Level bits (No Protection (other than BWRP))
#pragma config BSEN = OFF                                                       // Boot Segment Control bit (No Boot Segment)
#pragma config GWRP = OFF                                                       // General Segment Write-Protect bit (General Segment may be written)
#pragma config GSS = DISABLED                                                   // General Segment Code-Protect Level bits (No Protection (other than GWRP))
#pragma config CWRP = OFF                                                       // Configuration Segment Write-Protect bit (Configuration Segment may be written)
#pragma config CSS = DISABLED                                                   // Configuration Segment Code-Protect Level bits (No Protection (other than CWRP))
#pragma config AIVTDIS = OFF                                                    // Alternate Interrupt Vector Table bit (Disabled AIVT)

// FBSLIM
#pragma config BSLIM = 0x1FFF                                                   // Boot Segment Flash Page Address Limit bits (Enter Hexadecimal value)

// FOSCSEL
#pragma config FNOSC = PRIPLL                                                   // Oscillator Source Selection (Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL))
#pragma config PLLMODE = PLL96DIV4                                              // PLL Mode Selection (96 MHz PLL. Oscillator input is divided by 4 (16 MHz input))
#pragma config IESO = OFF                                                       // Two-speed Oscillator Start-up Enable bit (Start up with user-selected oscillator source)

// FOSC
#pragma config POSCMD = HS                                                      // Primary Oscillator Mode Select bits (HS Crystal Oscillator Mode)
#pragma config OSCIOFCN = ON                                                    // OSC2 Pin Function bit (OSC2 is general purpose digital I/O pin)
#pragma config SOSCSEL = OFF                                                    // SOSC Power Selection Configuration bits (Digital (SCLKI) mode)
#pragma config PLLSS = PLL_PRI                                                  // PLL Secondary Selection Configuration bit (PLL is fed by the Primary oscillator)
#pragma config IOL1WAY = OFF                                                    // Peripheral pin select configuration bit (Allow multiple reconfigurations)
#pragma config FCKSM = CSDCMD                                                   // Clock Switching Mode bits (Both Clock switching and Fail-safe Clock Monitor are disabled)

// FWDT
#pragma config WDTPS = PS1                                                      // Watchdog Timer Postscaler bits (1:1)
#pragma config FWPSA = PR32                                                     // Watchdog Timer Prescaler bit (1:32)
#pragma config FWDTEN = OFF                                                     // Watchdog Timer Enable bits (WDT and SWDTEN disabled)
#pragma config WINDIS = OFF                                                     // Watchdog Timer Window Enable bit (Watchdog Timer in Non-Window mode)
#pragma config WDTWIN = WIN50                                                   // Watchdog Timer Window Select bits (WDT Window is 50% of WDT period)
#pragma config WDTCMX = WDTCLK                                                  // WDT MUX Source Select bits (WDT clock source is determined by the WDTCLK Configuration bits)
#pragma config WDTCLK = SYSCLK                                                  // WDT Clock Source Select bits (WDT uses system clock when active, LPRC while in Sleep mode)

// FPOR
#pragma config BOREN = OFF                                                      // Brown Out Enable bit (Brown Out Disabled)
#pragma config LPCFG = OFF                                                      // Low power regulator control (No Retention Sleep)
#pragma config DNVPEN = DISABLE                                                 // Downside Voltage Protection Enable bit (Downside protection disabled when BOR is inactive)

// FICD
#pragma config ICS = PGD1                                                       // ICD Communication Channel Select bits (Communicate on PGEC1 and PGED1)
#pragma config JTAGEN = OFF                                                     // JTAG Enable bit (JTAG is disabled)

// FDEVOPT1
#pragma config ALTCMPI = DISABLE                                                // Alternate Comparator Input Enable bit (C1INC, C2INC, and C3INC are on their standard pin locations)
#pragma config TMPRPIN = OFF                                                    // Tamper Pin Enable bit (TMPRN pin function is disabled)
#pragma config SOSCHP = ON                                                      // SOSC High Power Enable bit (valid only when SOSCSEL = 1 (Enable SOSC high power mode (default))
#pragma config ALTI2C1 = ALTI2CEN                                               // Alternate I2C pin Location (SDA1 and SCL1 on RB9 and RB8)

/************************* Configuration Bits (end) ***************************/

#define FCY 16000000                                                            // FCY = FOSC / 2 (FCY: Instruction clock cycle) (FOSC: System clock cycle)

#include <libpic30.h>                                                           // Delay functions
#include <xc.h>                                                                 // MCU pin mapping
#include "L86-M33.h"                                                            // GNSS Receiver: Quectel L86-M33

int main(void)                           
{

    // Set pin direction
    TRISBbits.TRISB8 = 1;                                                       // Set MCU Pin #17 to input (I2C1 SCL1)
    TRISBbits.TRISB9 = 1;                                                       // Set MCU Pin #18 to input (I2C1 SDA1)
    TRISBbits.TRISB6 = 1;                                                       // Set MCU Pin #15 to input (UART1 RX)
    TRISBbits.TRISB7 = 0;                                                       // Set MCU Pin #16 to output (UART1 TX)    
    
    /************************ configure MCU modules *************************/

    // Analog Ports
    ANSA = 0;                                                                   // Disable A (PIC24FJ256GA702 datasheet p.126 Table 11-1)
    ANSB = 0;
    
    // Comparators
    CM1CONbits.CEN = 0;                                                         // Disable #1 (PIC24FJ256GA702 datasheet p.310 Register 25-1)
    CM2CONbits.CEN = 0;                                                         
    CM3CONbits.CEN = 0;                                                         
  
    // ADC
    AD1CON1bits.ADON = 0;                                                       // Disable module (PIC24FJ256GA702 datasheet p.291 Register 24-1) 

    // UART1
    RPINR18bits.U1RXR = 6;                                                      // Assign UART1 RX to RP6 (MCU Pin #15) (PIC24FJ256GA702 datasheet p.146 Register 11-23)
    RPOR3bits.RP7R = 3;                                                         // Assign UART1 TX to RP7 (MCU Pin #16) (PIC24FJ256GA702 datasheet p.152 Register 11-35)
    U1BRG = 103;                                                                // Baud rate (9600bps)(PIC24FJ256GA702 datasheet p.229 Eqn.19-1)
    U1MODEbits.UARTEN = 1;                                                      // Enable module (PIC24FJ256GA702 datasheet p.231 Register 19-1)
    U1STAbits.URXEN = 1;                                                        // Enable RX (PIC24FJ256GA702 datasheet p.233 Register 19-2)
    U1STAbits.UTXEN = 1;                                                        // Enable TX

    /********************* configure MCU modules (end) **********************/   

    PMTK_CMD_FULL_COLD_START();                                                 // Set operating conditions for L86-M33 (factory settings)
    
    while(1)
    {      
                                                                                // Empty loop
    }
    
    return 0;
    
}

The following steps must be taken before testing can take place:

  1. Insert one of the APC220 modules, with the USB to TTL adapter, to a USB port of a computer.
  2. Install the PowerGPS software and run as an administrator.
Testing

Connect one APC220 radio module to a USB port of a computer and run the PowerGPS software as an administrator, as shown in Figure 1.

Figure 1: Power GPS Main Screen

Select the COM port associated with the APC220 module (1). Press the “Create Connection” button to enable data collection (2).

Figure 2: Power GPS Data Acquisition

Wait for approximately 80 seconds for the L86-M33 receiver to acquire satellite data, as indicated by the “Statistics” window in the bottom left-hand quadrant. This is assuming the circuit is powered right after the Power GPS software is opened. The “SkyView” window, top left-hand quadrant, indicates the number and positions of satellites in view. In this case, there are a total of 14 satellites in view, also indicated in the “NMEA Text” window, “Sat in View,” in the bottom right-hand quadrant. As mentioned in the GNSS theory, latitude and longitude are represented in degrees and minutes, i.e., ddmm.mmmm and dddmm.mmmm, respectively. Looking at the “NMEA Text” window, latitude and longitude data can be found in the second and third lines, respectively. An example of a coordinate is Latitude: -33.8525356161454 and Longitude: 151.21061592481834, which is the Sydney Harbour Bridge. Other location-based data can be seen down the “NMEA Text” list. Other commands can be sent to the L86-M33 receiver to only display specific data.

Conclusion

Based on the display of GPS data via the PowerGPS software, the L86-M33 receiver is functioning as expected and can be used for the basis of projects.